• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    A method of modifying the state of stress of a semiconductor structure comprising the steps of: a) providing on a substrate the semiconductor structure (17) formed of a semiconductor stack comprising an alternation of elements based on of the first semiconductor material (13) and elements based on the second semiconductor material (15), then b) removing in the first structure (17) portions of the second semiconductor material so as to form spaces empty, c) filling the void spaces with a dielectric material (25) d) forming, on the first structure: a constraint zone (31) based on a first constrained material (33), e) performing a thermal annealing adapted to cause the dielectric material (25) to flow or relax, and to cause a change in the stress state of the elements based on the first semiconductor material (13) in the structure (17)
    公开号:FR3033081A1
    申请号:FR1551566
    申请日:2015-02-24
    公开日:2016-08-26
    发明作者:Sylvain Maitrejean；Emmanuel Augendre；Jean-Charles Barbe；Benoit Mathieu；Yves Morand
    申请人:Commissariat a lEnergie Atomique CEA；Commissariat a lEnergie Atomique et aux Energies Alternatives CEA；
    IPC主号:
    专利说明:

    [0001] TECHNICAL FIELD AND PRIOR ART The present invention relates to the field of microelectronics and more particularly to that of transistors equipped with a transistor. a stepped channel semiconductor structure, that is to say formed of semiconductor elements, such as nano-wires, or bars, or membranes, disposed therein s over others. To improve the performance of the transistors, it is possible to provide their channel region in a semiconductor material having a mechanical stress in tension or in compression.
    [0002] A voltage constraint induced, for example, in a silicon transistor channel makes it possible to obtain an increase in the speed of the electrons, whereas when a silicon channel undergoes a compressive stress, the speed of conduction by holes is increased. It is known to provide a microelectronic device comprising on the same substrate a first N-type transistor with planar channel structure provided in a material having a voltage stress and a second P-type transistor having a channel region in a relaxed material or having a compressive stress. Document US2008 / 0169508A1 gives an example of a method in which silicon blocks are constrained differently on the same substrate. To improve the control of the transistor channel and improve their integration density, it is known to fabricate transistor transistor channel structures. There is the problem of being able to modulate the state of constraint of such structures.
    [0003] SUMMARY OF THE INVENTION One embodiment of the present invention relates to a method for modifying the state of stress of a stepped channel structure of a first transistor, this structure being formed of semicircular elements. conductors arranged one above the other, the method comprising the steps of: a) providing on a substrate at least a first semiconductor structure formed of a semiconductor stack comprising alternating elements based on at least one first semiconductor material and elements based on at least one second semiconductor material different from the first semiconductor material, then b) selectively etching portions of the second semiconductor material, the removed portions. of the second semiconductor material forming one or more voids, c) filling the voids with a dielectric material, d) forming, on the first st structure: a stressing zone based on a first constrained material having an intrinsic stress, e) performing a thermal annealing adapted so as to flow the dielectric material, and cause a modification of a stress state of the elements to base of the first semiconductor material in the first structure.
    [0004] Such a method is adapted to the manufacture of a device having the first transistor and at least one second transistor having a second semiconductor element channel structure arranged one above the other, the second semi structure -conductor being provided in step a) in the semiconductor stack and also comprising an alternation of elements based on at least a first semiconductor material. In this case, the step d) of making the stressing zone may comprise steps of: depositing the first constrained material on the first structure and on the second structure, and then withdrawing the first constrained material on the second structure. The first structure of the first transistor and the second structure of the second transistor can thus be constrained differently. The method may further comprise forming on the second structure another strain zone based on a second constrained material having an intrinsic stress opposite that of the first constrained material. By opposite constraint is meant that when the first material constrained to an intrinsic stress in tension, the second material constrained has an intrinsic stress in compression and vice versa. The realization of this other constraint zone may comprise steps of: depositing the second constrained material on the first structure and on the second structure, and then removing the second constrained material on the first structure. It is then possible to carry out a thermal annealing adapted to make the dielectric material flow, and to cause a modification of a state of stress of the elements based on the first semiconductor material in the second structure. This annealing can be carried out during step e), at the same time as that used to modify the state of stress of the first structure. According to one possible implementation of the method, the first structure and the second structure provided in step a) can be attached to each other by means of at least one anchor block. This anchor block can be removed prior to step e). Advantageously, the anchor block can be removed after step d) of forming the etching stress zone using this zone. constraint as a protective mask to this engraving. According to one possible implementation of the method, the substrate provided in step a) may be a constrained semiconductor-on-insulator substrate having a stressed surface semiconductor layer. In this case, the state change of constraint 3033081 in step e) may consist of a relaxation of the elements based on the first semiconductor material. According to another possibility of implementing the method, the substrate provided in step a) may be an insulator-constrained semiconductor substrate having a relaxed surface semiconductor layer. In this case, the change of stress state in step e) may consist of an increase in a state of stress in tension or in compression induced by the stressing zone in the elements based on the first semi material -driver. When the stressing zone is intended to induce a voltage stress in the elements based on the first semiconductor material, the stress state change in step e) may be an increase in the voltage stress. in the elements based on the first semiconductor material. According to one possible embodiment of the method, the dielectric material for filling the void spaces may be based on SiO 2 or silicon oxide doped in particular with the boron and / or phosphorus. According to one possibility of implementing the method, the first semiconductor material may be Si whereas the second semiconductor material is SiXx-x with x> 0. According to one possibility of implementing the method, the first material 20 semiconductor can be Sii_yGey with y> 0 while the second semiconductor material is Si. BRIEF DESCRIPTION OF THE DRAWINGS The present invention will be better understood on reading the description of exemplary embodiments given, for information only and in no way limiting, with reference to the accompanying drawings in which: FIGS. 1A-1M illustrate a first example of a method according to an embodiment of the invention, for relaxing a semiconductor structure with channel stages of a first transistor; FIGS. 2A-2B illustrate an alternative embodiment of the first exemplary method; FIGS. 3A-3C illustrate a second example of a method for increasing the stress in a channel-stage semiconductor structure of a second transistor; FIG. 4 illustrates a variant in which the first example and the second example of a method are combined in order to relax a semiconductor structure with channel stages of a first transistor while increasing the stress in a semiconductor structure with channel stages. a second transistor; Identical, similar or equivalent parts of the different figures bear the same numerical references in order to facilitate the passage from one figure to another. The different parts shown in the figures are not necessarily in a uniform scale to make the figures more readable.
    [0005] In addition, in the description below, terms that depend on the orientation, such as "on", "above", "upper", "lateral" etc. of a structure apply considering that the structure is oriented in the manner illustrated in the figures. DETAILED DESCRIPTION OF PARTICULAR EMBODIMENTS An exemplary method for producing a device having a first stage channel structure of a transistor of a first type and a second stage channel structure of a transistor of a second type, will now be described in connection with Figures 1A-1M. FIGS. 1A-1C illustrate a possible starting device for producing this exemplary method from a semiconductor substrate constrained on an insulator, for example of the type sS01 (for "strained silicon on the insulator" or "constrained silicon"). on insulator). This substrate thus comprises a semiconductor support layer 10 coated with an insulating layer 11 which may be based on silicon oxide. The substrate 3033081 6 also comprises a so-called "superficial" semiconductive layer 12 situated on and in contact with the insulating layer 11. The semiconducting layer 12 is based on a first crystalline semiconductor material 13. In this example, the crystalline semiconductor material 13 is constrained and can be, for example, voltage-constrained silicon. Several other semiconductor layers are formed on the superficial semiconductor layer 12, for example by several successive epitaxies, and form with the latter a semiconductor stack. The semiconductor stack is composed of an alternation of one or more layers 12 based on the first semiconductor material 13 and one or more layers 14, based on a second semiconductor material 15. The second Semiconductor material 15 is different from the first semiconductor material 13 and can be selected so that it can be etched selectively with respect to the first semiconductor material. The second semiconductor material 15 may be for example Sii_xGex with x> 0.
    [0006] Once the semiconductor stack is formed, the layers 12, 14 of the latter are etched so as to form at least one semiconductor structure 17 comprising alternating semiconductor elements 201, 202, ..., 20k, 20k + 1 superimposed based on the first semiconductor material 13 and the second semiconductor material 15, and at least one other structure 19 comprising an alternation 20 of superimposed semiconductor elements 201, 202, ..., 20k, 20k + 1 based on the first semiconductor material 13 and the second semiconductor material 15. According to the ratio between their widths W and their respective lengths L, the semiconductor elements 201, 202, ..., 20k, 20k +1, may be for example in the form of nano-son, or bars, or membranes parallel to the main plane of the substrate. The main plane 25 of the substrate is here defined as a plane passing through the latter and which is parallel to the plane [0; x; y] orthogonal reference [0; x; y; z] given in the figures. The structures 17 and 19 can be attached to each other via at least one anchoring block 18 also formed in the stack of semiconductor layers 12, 14.
    [0007] The structure 17 is provided on the substrate in a region R1 in which one or more transistors of a given type, for example type P are provided, while the other structure 19 is formed on the substrate in another region. R2 in which one or more transistors of another type, for example type N are provided.
    [0008] Due to the initial stress of the surface layer 12 of the substrate, the semiconductor elements 201, 203, ..., 20k + 1, based on the first semiconductor material 13 in the structures 17 and 19 are constrained, for example in tension. In FIG. 1A, the semiconductor structures 17 and 19 are shown in plan view, while in FIG. 1B only the structure 17 is shown in a cross-sectional view B'B. FIG. 1C gives, for its part, a longitudinal sectional view A'A of this same structure 17. The second semiconductor material 15 is then selectively etched with respect to the first semiconductor material 13. in order to at least partially remove the second semiconductor material 15 from the structure 17 and possibly from the other structure 19 when the latter is also unveiled during this etching (FIGS. 1D and 1E). When the second semiconductor material 15 is Sii_xGex, its removal can be carried out for example using an isotropic etching based on CF4 + Oz plasma.
    [0009] In the structures 17 and 19, portions removed from the second semiconductor material 15 form voids 21 between the elements 201, 203, ..., 20k + 1, based on the first semiconductor material 13. To maintain the structures 17, 19 despite this etching, anchor blocks 18 at their ends may be provided with dimensions in a plane parallel to the main plane of the substrate larger than those W, L of the structures 17, 19. Thus, the selective etching of the second semiconductor material 15 is preferably carried out so that areas based on the second semiconductor material 15 are retained in the anchor blocks 18. The anchor blocks 18 may be sacrificial and located at locations of future source and drain blocks of the transistors.
    [0010] The empty spaces 21 are then filled with a dielectric material such as, for example, SiO 2 or boron-doped and / or phosphorus-doped silicon oxide (FIGS. 1F and 1G). Partial etching of the dielectric material 25 and selective with respect to the first semiconductor material 13 can then be performed to form insulators 261,..., 26n (n an integer such that n> 1) of replacing substantially the same dimensions as the elements 202, ..., 20k based on the second semiconductor material which have just been removed. In one case, for example, where the dielectric material 25 is SiO 2 and the first semiconductor material 13 is Si, this etching can be carried out for example using CHF 3 in an ICP (inductive coupled plasma) reactor. as described in NR Rueger, et al. J. Vac. Sci. Technol. At this stage of the process, the semiconductor elements 201, 203,..., 20k + 1 based on the first semiconductor 13 can be voltage-stressed, while that the insulative elements 261,..., 26n based on a dielectric material 25 may be subject to a slight compressive stress. The anchoring block (s) 18 and in particular that separating the structures 17 and 19 can then be removed (FIGS. 1H and 11). This can be achieved by means of photolithography and etching steps through a mask provided with one or more openings revealing the anchor blocks 18. Next, the structure 17 is formed with a stress-relieving zone 31. a material 33 having intrinsic stress. In this example, the material 33 is a voltage-constrained dielectric material, for example SixNy voltage-stressed. In this embodiment where it is desired to relax the structure 17, the stress zone 31 is designed to apply a stress in the material 13 of the semiconductor elements 201, 203, ..., 20k + 1 which opposes that of the surface layer 12 and in the semiconductor elements 201, 203, ..., 20k + 1 after growth of the stack of semiconductor layers. The stressing zone 31 is formed on the region R1 in which one or more N-type transistors are provided.
    [0011] At the same time, where it is intended to maintain a constraint in the other structure 19, the stressing zone 31 is not provided for or maintained on this other structure 19. To obtain such an arrangement, the material 33 can be deposited on the R1 and R2 regions and then removed in relation to the other region R2, for example by photolithography and etching. The stressing zone 31 thus formed covers the structure 17 and extends in particular on an upper face 17a and side faces 17b, 17c of the structure 17, while the other structure 19 is not covered by this zone 31 (FIGS. 1J, 1K, and 1L). Thereafter, thermal annealing is carried out, the temperature and duration of which are provided so as to modify the viscoelastic behavior of the dielectric material 25 so as to cause it to flow and to relax. This creep is capable of causing a modification of the state of stress in the elements 201, 203,..., 20k + 1 of the first structure 17 which are based on the first semiconductor material 13. The thermal annealing of the Dielectric material 25 may be provided at a temperature and time suitable to allow the semiconductor material 13 to undergo a strain variation of at least 1GPa if one starts from a substrate SS01 with a stress of 1.4 GPa.
    [0012] Such annealing may be carried out for example at a temperature of between 1000 ° C. and 1400 ° C. for a duration of for example of the order of 2 hours when the dielectric material 25 produced is SiO 2. When the dielectric material 25 is based on silicon oxide doped for example with phosphorus or boron or with phosphorus and boron such as BPSG (for "Boron and Phosphorous Doped Glass"), a lower temperature range of annealing can be advantageously used. For example, an annealing may be carried out at a temperature of between 500 ° C. and 800 ° C. for a duration of for example of the order of 2 hours when the dielectric material 25 is BPSG.
    [0013] In this embodiment, by virtue of the thermal creep annealing of the dielectric material 25, the elements 201, 203,..., 20k + 1 of the structure 17 which are based on the first semiconductor material 13 initially constrained by tension are relaxed. With the aid of such annealing, the effect of the stressing zone 31 on the structure 17 is thus amplified. Once the annealing has been carried out, the stress-relieving zone 31 can then be removed from the material. This removal can be carried out for example by wet etching with the aid of hot phosphoric acid when the material 33 is based on silicon nitride.
    [0014] In this embodiment, a relaxed structure 17 is thus formed in the region R1 of the substrate intended to form a channel region of a P-type transistor, while in the region R2 a voltage-constrained structure 19 is maintained for to form a channel region of an N-type transistor. The formation of the transistors can then be completed by making one or more blocks 501,..., 50m, gates on the structure 17 and one or more blocks 501, ..., 50i on the other structure 19 (Figure 1M). These blocks 501, ..., 50m, grids can be arranged against the side faces and the upper face of the structures 17 and 19 so as to coat them. In the exemplary embodiment illustrated in FIGS. 1A-1M, the channel regions 20 of the N-type transistor type Pet transistor are respectively formed of several juxtaposed semiconductor structures identical to the structure 17 and of several semicircular structures. The number of semiconductor structures to form the channel region of the transistors is not limited and may possibly vary from one transistor to another.
    [0015] An alternative to the exemplary method just described is illustrated in FIGS. 2A-2B. For this variant, the step of removing the anchoring block or blocks 18 disposed between the semiconductor structures 17 and 19 is postponed. Once the steps previously described in connection with FIGS. 1A-1G have been completed and portions have been replaced, of the second semiconductor material 30 by the dielectric material 25 between the elements based on the first semiconductive material 13, the stressing zone 31 is formed. For this, the material 33 based on material 33 having an intrinsic elastic stress is deposited on the regions R1 and R2 (Figure 2A). Subsequently, this material 33 is withdrawn in an area facing the one or more anchoring blocks 18. The anchoring block (s) 18 can then be removed by etching using the stressing zone 31 as shown in FIG. a protective mask for engraving. Then, the material 33 is withdrawn opposite the other region R2 (FIG. 2B).
    [0016] Another exemplary embodiment, illustrated in FIGS. 3A-3B, provides after carrying out the steps previously described in connection with FIGS. 1A-11 and removed the anchoring block (s) 18, to make a zone 132 for the implementation of FIG. constraint on the region R2 in which one or more N-type transistors are provided. The stressing zone 132 is this time based on a material 134 having an intrinsic stress opposite to that used in the previous examples and formed on the first region R1. In this example, the stressing zone 132 is a zone based on a dielectric material 134 which is constrained in compression, such as, for example, compression-stressed SiXNV. In order to form this zone 132, the material 134 can be deposited on the regions R2 and R1 and then removed opposite the region R1, for example by photolithography and etching. Figure 3A gives a top view of the device in progress. In Figures 3B and 3C only the other structure 19 is shown respectively in a cross-sectional view and in longitudinal section. In this example, the stressing zone 132 makes it possible to create a voltage stress in the elements based on the first semiconductor material 13 of the other structure 19. Next, the thermal annealing step is carried out at a high temperature. temperature so as to flow or relax the dielectric material interposed between the elements based on the first semiconductor material 13.
    [0017] The creep or relaxation of the dielectric material 25 causes a modification of the stress in the elements based on the first semiconductor material 13 of the other structure 19. Such annealing may be carried out for example at a temperature of between 1000 ° C. C and 1400 ° C for a duration for example of the order of 2h when the dielectric material 25 is made of SiO 2. By virtue of the creep of the dielectric material 25, the voltage stress generated by means of the stressing zone 132 in the elements of the structure 19 which are based on the first semiconductor material 13 is increased.
    [0018] Thus, in the embodiment which has just been described, the stress modification obtained by thermal annealing of the dielectric material 25 makes it possible to increase a voltage stress induced in the structure 19 of the N-type transistor or transistors. Another exemplary embodiment illustrated in connection with FIGS. 1A-1C can be combined with that described in connection with FIGS. 1K-1M to allow the structure 17 to be relaxed and to further constrain the structure 19. The steps described in connection with FIGS. FIGS. 3A-3C may thus be made before those described in connection with FIGS. 1K-1M or after those described with reference to FIGS. 1K-1M.
    [0019] In the exemplary embodiment illustrated in FIG. 4, in the region R1, on the structure 17, a stressing zone 31 is formed based on a material 33 having an intrinsic stress in tension, for example silicon nitride. while in the region R2 is formed on the other structure 19 another stressing zone 132 based on a material 434 having an intrinsic stress opposite 25 for example silicon nitride constrained in compression. Next, the annealing is carried out so as to flow the dielectric material 25 into the structures 17 and 19 and impose a compressive stress in the semiconductor of the structure 17 while increasing the voltage stress in the semiconductor of the structure 19.
    [0020] It is also possible, as a variant of the example of the method described above in connection with FIGS. 1A-1M, to compress the structure 17 in compression. The starting substrate can in this case be an SOI type substrate with a superficial layer 12 relaxed.
    [0021] An alternative embodiment of the embodiment which has been previously described in connection with FIGS. 3A-3C provides starting from a SiGe01-type substrate, this time with a SiGe-based surface layer 12. The semiconductor stack from which the structures 17, 19 are made can in this case be formed of an alternation of layers 12 based on Sii_yGey with 10 y> 0 and layers 14 based on Si. , the selective etching removal of the second semiconductor material 15 in the structures 17, 19 may be carried out for example by means of a method as described for example in the document by Stéphan Borel et al. "Control de selectivity between SiGe and Si in Isotropic Etching Processes", Japanese Journal of Applied Physics, 2004. A voltage stress zone, for example voltage-constrained nitride, is then formed on the structure 19 in order to to constrain in compression. Then, the thermal creep or relaxation annealing of the dielectric material 25 is carried out in order to increase the compressive stress in this structure 19. An alternative embodiment of the exemplary embodiment which has been described previously with reference to FIGS. 1A -1M provides starting from a sSiGe01 type substrate, this time with a surface layer 12 based on SiGe having an intrinsic compressive stress. Then, in the case where it is desired to relax a structure 17, there is formed thereon a stress zone in compression, for example nitride constrained in compression before performing the thermal annealing creep or relaxation of the dielectric material 25. 30
    权利要求:
    Claims (9)
    [0001]
    REVENDICATIONS1. A method of making a microelectronic device having at least a first transistor having a first semiconductor element channel structure (17, 19) arranged one above the other, the method comprising the steps of: a ) providing on a substrate, at least one first semiconductor structure (17, 19) formed of a semiconductor stack comprising an alternation of elements based on at least a first semiconductor material (13) and elements based on at least one second semiconductor material (15) different from the first semiconductor material, then b) removing in the first structure (17, 19), by selective etching: portions of the second semiconductor material, the portions removed from the second semiconductor material forming one or more voids (21); c) filling the void spaces with a dielectric material (25); d) forming, on the first structure: a zone (31); , 132) of stress-based on a first constrained material (33, 134) having an intrinsic stress, e) performing a thermal annealing adapted to flow the dielectric material (25), and cause a modification of the stress state of the elements based on the first semiconductor material (13) in the first structure (17).
    [0002]
    2. Method according to claim 1, wherein the microelectronic device is provided with at least one second transistor having a second channel structure with semiconductor elements arranged one above the other, at least one second semiconductor structure. (19, 17) formed in the semiconductor stack and comprising an alternation of elements based on at least a first semiconductor material (13) and elements based on at least one second semiconductor material ( 15) different from the first semiconductor material being provided in step a), step d) comprising steps of: depositing the constrained material (33, 134) on the first structure and on the second structure, and then - removing the first constrained material on the second structure. 5
    [0003]
    The method of claim 2, further comprising the steps of: forming on the second structure: a stressing zone based on a second constrained material having an intrinsic stress opposite to that of the first constrained material.
    [0004]
    4. Method according to one of claims 2 or 3, wherein the first structure and the second structure provided in step a) are attached through at least one anchor block (18), the block of anchoring being removed prior to step e).
    [0005]
    5. The method of claim 4, wherein the anchor block is removed after step d) by etching using the stressing area as a protective mask to this etching. 20
    [0006]
    6. Method according to one of claims 1 to 5, wherein the substrate provided in step a) is a substrate of semiconductor type constrained on insulator with a surface semiconductor layer (12) stress, the stress state modification in step e) being a relaxation of the elements based on the first semiconductor material (13).
    [0007]
    7. Method according to one of claims 1 to 5, wherein the substrate provided in step a) is a semiconductor-on-insulator substrate having a relaxed surface semiconductor layer, the state modification. The step e) is an increase of a state of stress induced by the stress zone (31) in the elements based on the first semiconductor material (13).
    [0008]
    The method of one of claims 1 to 7, wherein the dielectric material is based on SiO 2 or doped silicon oxide.
    [0009]
    Method according to one of claims 1 to 8, wherein the first semiconductor material (13) is Si while the second semiconductor material (15) is Sii_yGey with y> 0 or in which the first semi material The conductor (13) is at Si1_xGex with x> 0, while the second semiconductor material (15) is Si.
    类似技术:
    公开号 | 公开日 | 专利标题
    EP3062350B1|2018-03-14|Method for modifying the state of stress of a semiconductor structure with transistor channel stages
    EP2075826B1|2013-08-07|Method of manufacturing a semiconductor-on-insulant substrate comprising a step with localised Ge enrichment
    EP1869712B1|2012-07-18|Structure and method for realizing a microelectronic device provided with a number of quantum wires capable of forming one or more transistor channels
    EP3070744B1|2017-07-05|Improved method for producing a transistor in a stack of superposed semiconductor layers
    EP2835832A2|2015-02-11|Improved method for producing doped areas and/or exerting a stress on the spacers of a transistor
    EP1638149B1|2011-11-23|Method of manufacture of an heterostructure channel insulated gate field effect transistor
    EP2887384A1|2015-06-24|Improved method for producing stressed semiconductor blocks on the insulating layer of a semiconductor on insulator substrate
    EP2562804B1|2014-06-18|Method for making a device comprising transistors strained by silicidation of source and drain regions, and device
    FR3051970A1|2017-12-01|IMPLEMENTING A SHAPED CHANNEL STRUCTURE OF A PLURALITY OF CONTAINING SEMICONDUCTOR BARS
    FR3057702A1|2018-04-20|METHOD FOR MANUFACTURING A COILGROUND FIELD EFFECT TRANSISTOR
    FR2910456A1|2008-06-27|METHOD FOR PRODUCING MICROFILS AND / OR NANOWIAS
    FR3057703B1|2019-06-28|METHOD FOR MANUFACTURING A COILGROUND FIELD EFFECT TRANSISTOR
    FR3005309A1|2014-11-07|NANOWELL AND PLANNER TRANSISTORS COINTEGRATED ON SUBSTRATE SOI UTBOX
    EP2610915A1|2013-07-03|Transistor and method for manufacturing a transistor
    EP3026711B1|2019-12-25|Improved method for inducing strain in a transistor channel using sacrificial source/drain regions and a gate replacement
    FR3048815A1|2017-09-15|METHOD FOR CO-REALIZATION OF ZONES UNDER DIFFERENT UNIAXIAL CONSTRAINTS
    FR3073667A1|2019-05-17|3D CIRCUIT WITH TRANSISTORS WITHOUT JUNCTION N AND P
    EP3142151B1|2018-03-07|Method for producing an uniaxially stressed transistor channel structure
    FR3048816A1|2017-09-15|METHOD FOR MANUFACTURING DEVICE WITH VOLTAGE CONSTANT NMOS TRANSISTOR AND PMOS TRANSISTOR CONSTRAINED IN UNI-AXIAL COMPRESSION
    FR3050315B1|2019-06-21|TRANSISTOR A OVERLAP OF MASTER ACCESS REGIONS
    EP3026712B1|2020-07-15|Improved method for straining a region of a transistor channel
    EP3511293A1|2019-07-17|Method for manufacturing at least one field-effect transistor
    EP3503175A1|2019-06-26|Method for producing a semiconductor substrate comprising at least one portion of semiconductor subjected to compressive strain
    EP3442027A1|2019-02-13|Method for forming doped extension regions in a structure having stacked nanowires
    FR3050569A1|2017-10-27|IMPROVED SILICON FABRICATION CONSTANT TO VOLTAGE THROUGH INSULATION BY AMORPHIZATION THEN RECRYSTALLIZATION
    同族专利:
    公开号 | 公开日
    US9853130B2|2017-12-26|
    EP3062350A1|2016-08-31|
    US20160254362A1|2016-09-01|
    EP3062350B1|2018-03-14|
    FR3033081B1|2017-03-31|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    WO2013095341A1|2011-12-19|2013-06-27|Intel Corporation|Cmos implementation of germanium and iii-v nanowires and nanoribbons in gate-all-around architecture|
    US20140097502A1|2012-10-10|2014-04-10|Seoul National University R & Db Foundation|Semiconductor device and fabricating method thereof|
    US20140099793A1|2012-10-10|2014-04-10|Seoul National University R&Db Foundation|Semiconductor device and method for fabricating the same|
    US20150044826A1|2013-08-06|2015-02-12|Stmicroelectronics Sa|Method of introducing local stress in a semiconductor layer|
    US7118987B2|2004-01-29|2006-10-10|Taiwan Semiconductor Manufacturing Co., Ltd.|Method of achieving improved STI gap fill with reduced stress|
    US7888197B2|2007-01-11|2011-02-15|International Business Machines Corporation|Method of forming stressed SOI FET having doped glass box layer using sacrificial stressed layer|
    KR101835114B1|2011-09-07|2018-03-06|삼성전자주식회사|Three Dimensional Semiconductor Device And Method Of Fabricating The Same|
    CN103985751B|2013-02-08|2016-12-28|中国科学院微电子研究所|Quasiconductor is arranged and manufacture method|
    FR3005309B1|2013-05-02|2016-03-11|Commissariat Energie Atomique|NANOWELL AND PLANNER TRANSISTORS COINTEGRATED ON SUBSTRATE SOI UTBOX|
    KR102195112B1|2013-11-19|2020-12-24|삼성전자주식회사|Vertical memory devices and methods of manufacturing the same|
    FR3014244B1|2013-11-29|2018-05-25|Commissariat A L'energie Atomique Et Aux Energies Alternatives|IMPROVED METHOD FOR PRODUCING A CONDUCTIVE SEMICONDUCTOR SUBSTRATE ON INSULATION|
    FR3015769B1|2013-12-23|2017-08-11|Commissariat Energie Atomique|IMPROVED METHOD FOR PRODUCING CONCEALED SEMICONDUCTOR BLOCKS ON THE INSULATING LAYER OF A SEMICONDUCTOR SUBSTRATE ON INSULATION|
    FR3015768B1|2013-12-23|2017-08-11|Commissariat Energie Atomique|IMPROVED METHOD OF MODIFYING THE STRAIN STATUS OF A BLOCK OF SEMICONDUCTOR MATERIAL|
    FR3023411B1|2014-07-07|2017-12-22|Commissariat Energie Atomique|LOCALIZED GENERATION OF STRESS IN A SOIL SUBSTRATE|US20180158737A1|2015-06-27|2018-06-07|Intel Corporation|Integration method for finfet with tightly controlled multiple fin heights|
    FR3051970B1|2016-05-25|2020-06-12|Commissariat A L'energie Atomique Et Aux Energies Alternatives|REALIZATION OF A CHANNEL STRUCTURE FORMED OF A PLURALITY OF CONSTRAINED SEMICONDUCTOR BARS|
    FR3088480B1|2018-11-09|2020-12-04|Commissariat Energie Atomique|BONDING PROCESS WITH ELECTRONICALLY STIMULATED DESORPTION|
    FR3091619B1|2019-01-07|2021-01-29|Commissariat Energie Atomique|Healing process before transfer of a semiconductor layer|
    法律状态:
    2016-02-29| PLFP| Fee payment|Year of fee payment: 2 |
    2016-08-26| PLSC| Search report ready|Effective date: 20160826 |
    2017-02-28| PLFP| Fee payment|Year of fee payment: 3 |
    2018-02-26| PLFP| Fee payment|Year of fee payment: 4 |
    2019-10-25| ST| Notification of lapse|Effective date: 20191006 |
    优先权:
    申请号 | 申请日 | 专利标题
    FR1551566A|FR3033081B1|2015-02-24|2015-02-24|METHOD FOR MODIFYING THE STRAIN STATUS OF A SEMICONDUCTOR STRUCTURE WITH TRANSISTOR CHANNEL STAGES|FR1551566A| FR3033081B1|2015-02-24|2015-02-24|METHOD FOR MODIFYING THE STRAIN STATUS OF A SEMICONDUCTOR STRUCTURE WITH TRANSISTOR CHANNEL STAGES|
    US15/049,468| US9853130B2|2015-02-24|2016-02-22|Method of modifying the strain state of a semiconducting structure with stacked transistor channels|
    EP16156850.6A| EP3062350B1|2015-02-24|2016-02-23|Method for modifying the state of stress of a semiconductor structure with transistor channel stages|
    [返回顶部]